ATLAS hardware-based Endcap Muon Trigger for future upgrades

TL;DR

The paper presents the design and expected performance of a new hardware-based endcap muon trigger system for the ATLAS detector, aiming to handle increased data rates and improve trigger efficiency for future LHC upgrades.

Contribution

It introduces a novel trigger processor board with FPGA technology for hardware-based track reconstruction in the ATLAS endcap muon system.

Findings

Design of a new trigger processor board with FPGA

Expected improved trigger performance for Run 3 and HL-LHC

Enhanced data handling with full-granularity information

Abstract

The LHC is expected to increase its center-of-mass energy from 13 TeV to 14 TeV for Run 3 scheduled from 2022 to 2024. After Run 3, upgrades for the High-Luminosity-LHC (HL-LHC) programme are planned and the operation will start in 2027, increasing the instantaneous luminosity to 5.0 -- 7.5 times its nominal luminosity. Continuous upgrades of the ATLAS trigger system are planned to cope with the high event rate and to keep the physics acceptance. During the long shutdown period before Run 3, new detectors will be installed to improve the trigger performance. New trigger logic, combining information from detectors located outside of the magnetic field and new detectors installed inside the magnetic field, are introduced from Run 3 to reduce the trigger rate. In order to handle data from the various detectors, a new trigger processor board has been developed and the design is presented. During the upgrade for HL-LHC, the trigger and readout systems of the first level hardware-based part are planned to be upgraded. Full-granularity information will be transferred to the trigger processor board which enables more off-line like track reconstruction in the hardware-based system. To handle the full-granularity information and perform the hardware-based track reconstruction, the trigger processor board will implement an FPGA with hundreds of pairs of transceivers and huge memory resources. Expected performance for the hardware-based endcap muon trigger in Run 3 and HL-LHC will also be presented.