Efficient Floating-Point Givens Rotation Unit

TL;DR

This paper introduces an efficient floating-point Givens rotation unit for QR decomposition, optimized for embedded systems, with novel format enhancements and FPGA implementation showing significant improvements.

Contribution

It presents a high-throughput floating-point Givens rotation unit with a new Half-Unit Biased format, improving hardware efficiency for QR decomposition.

Findings

Significant reduction in area and latency compared to previous designs.

Enhanced throughput for embedded signal processing applications.

Effective error trade-offs demonstrated through analysis.

Abstract

High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. FPGA implementation results are also presented and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.