Conversion Gain Enhancement in Standard CMOS Image Sensors

TL;DR

This paper investigates methods to significantly improve the conversion gain in standard CMOS image sensors by combining process refinements and circuit design optimizations, leading to over threefold enhancement.

Contribution

It introduces novel CG enhancement techniques and demonstrates their effectiveness in a 180 nm CMOS process, providing insights into parasitic effects on sense node capacitance.

Findings

CG improved by more than a factor of 3

Enhanced understanding of parasitic elements affecting CG

Implementation in 180 nm process validates techniques

Abstract

This paper focuses on the conversion gain (CG) of pixels implementing pinned photo-diodes (PPD) and in-pixel voltage follower in standard CMOS image sensor (CIS) process. An overview of the CG expression and its impact on the noise performance of the CIS readout chain is presented. CG enhancement techniques involving process refinements and pure circuit design and pixel scheme optimization are introduced. The implementation of these techniques in a 180 nm CIS process demonstrates a progressive enhancement of the CG by more than a factor 3 with respect to a standard reference pixel from the same foundry, allowing a better understanding of the different parasitic elements on the sense node capacitance and CG.