MicroNets: Neural Network Architectures for Deploying TinyML Applications on Commodity Microcontrollers
Colby Banbury, Chuteng Zhou, Igor Fedorov, Ramon Matas Navarro, Urmish, Thakker, Dibakar Gope, Vijay Janapa Reddi, Matthew Mattina, Paul N. Whatmough

TL;DR
This paper introduces MicroNets, a neural architecture designed for TinyML applications on microcontrollers, using differentiable NAS to optimize for low memory, latency, and energy, achieving state-of-the-art results on standard benchmarks.
Contribution
The paper proposes a novel NAS approach exploiting a linear latency-op count relationship, resulting in efficient MicroNet models for TinyML deployment on MCUs.
Findings
MicroNets achieve state-of-the-art results on TinyMLperf benchmarks.
The linear relationship between latency and op count simplifies NAS for MCUs.
MicroNets are deployed successfully using Tensorflow Lite Micro.
Abstract
Executing machine learning workloads locally on resource constrained microcontrollers (MCUs) promises to drastically expand the application space of IoT. However, so-called TinyML presents severe technical challenges, as deep neural network inference demands a large compute and memory budget. To address this challenge, neural architecture search (NAS) promises to help design accurate ML models that meet the tight MCU memory, latency and energy constraints. A key component of NAS algorithms is their latency/energy model, i.e., the mapping from a given neural network architecture to its inference latency/energy on an MCU. In this paper, we observe an intriguing property of NAS search spaces for MCU model design: on average, model latency varies linearly with model operation (op) count under a uniform prior over models in the search space. Exploiting this insight, we employ differentiable…
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Taxonomy
TopicsAdvanced Neural Network Applications · Anomaly Detection Techniques and Applications · Machine Learning and Data Classification
MethodsDifferentiable Neural Architecture Search
