Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

TL;DR

This paper presents the design and testing of a high-bandwidth Global Trigger Demonstrator board for the ATLAS Phase-II upgrade, showcasing successful high-speed optical communication using advanced FPGAs and optical modules.

Contribution

It introduces a new hardware demonstrator for high-speed optical data transmission in the ATLAS trigger system upgrade, validating performance at data rates up to 28 Gb/s.

Findings

Successful long-run tests at 25.65 Gb/s and 27.58 Gb/s

Demonstrated reliable communication between FPGA and optical modules

Hardware overview and performance measurements provided

Abstract

ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at high data rates (up to 28 Gb/s), a Global Trigger Technological Demonstrator board has been designed and tested. The main hardware blocks of the board are the Xilinx Virtex Ultrascale+ 9P FPGA and a number of optical modules, including high-speed Finisar BOA and Samtec FireFly modules. Long-run link tests have been performed for the Finisar BOA and Samtec FireFly optical modules running at 25.65 and 27.58 Gb/s respectively. Successful results demonstrating a good performance of the optical modules when communicating with the FPGA have been obtained. The paper provides a hardware overview and measurement results of the Technological Demonstrator.