Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices

TL;DR

This paper discusses the importance of joint optimization of AI algorithms and hardware accelerators for edge devices, highlighting recent co-design methodologies and demonstrating their effectiveness through extensive experiments.

Contribution

It presents three innovative co-design methodologies for DNN and hardware accelerators, advancing the state-of-the-art in AI hardware-software integration.

Findings

Effective co-design methods outperform existing approaches

Demonstrated improvements on FPGA and GPU platforms

Highlights the significance of integrated algorithm-accelerator optimization

Abstract

High quality AI solutions require joint optimization of AI algorithms, such as deep neural networks (DNNs), and their hardware accelerators. To improve the overall solution quality as well as to boost the design productivity, efficient algorithm and accelerator co-design methodologies are indispensable. In this paper, we first discuss the motivations and challenges for the Algorithm/Accelerator co-design problem and then provide several effective solutions. Especially, we highlight three leading works of effective co-design methodologies: 1) the first simultaneous DNN/FPGA co-design method; 2) a bi-directional lightweight DNN and accelerator co-design method; 3) a differentiable and efficient DNN and accelerator co-search method. We demonstrate the effectiveness of the proposed co-design approaches using extensive experiments on both FPGAs and GPUs, with comparisons to existing works. This paper emphasizes the importance and efficacy of algorithm-accelerator co-design and calls for more research breakthroughs in this interesting and demanding area.