Ab-initio NEGF Perspective of Ultra-Scaled CMOS: From 2D-material Fundamentals to Novel Dynamically-Doped Transistors

TL;DR

This paper explores the potential of sub-10 nm CMOS scaling using advanced atomistic simulations, highlighting the benefits of 2D materials and a new dynamically-doped transistor design for ultra-scaled high-performance devices.

Contribution

It introduces a novel dynamically-doped FET concept and demonstrates the feasibility of using 2D materials like HfS2 for sub-10 nm CMOS scaling.

Findings

High drive current achievable at ~6 nm with 2D materials

Dynamically-Doped FET outperforms traditional MOSFET at extreme scales

Scaling down to 1 nm gate length with high performance is feasible

Abstract

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of good electrostatic control together with a high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10 nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge or III-V and dimensional scaling is expected to end around 12 nm gate-length. We demonstrate that using alternative 2D channel materials, such as the less explored HfS2 or ZrS2, high-drive current down to about 6 nm is, however, achievable. We also propose a novel transistor concept, the Dynamically-Doped Field-Effect Transistor, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to 1 nm gate length using a single-gate architecture and an ultra-compact design. The Dynamically-Doped Field-Effect Transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.