A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA

TL;DR

This paper presents a high-resolution multi-phase Time-Digital Converter implemented on Kintex-7 FPGA, achieving a significant reduction in bin size and improved time resolution for pulse signal measurement.

Contribution

The work introduces a novel multi-phase TDC design on Kintex-7 FPGA with a simplified input buffer and ISERDES core, achieving sub-100 ps bin size and enhanced measurement accuracy.

Findings

Effective bin size reduced from 625 ps to 78.125 ps

Dual-channel time resolution better than 35 ps RMS

Successful FPGA implementation and verification

Abstract

Time-digital Converter (TDC) aims to measure the arrival time of the leading edge of the pulse signal. Our recent work presented a high resolution multi-phase TDC based on the Kintex-7 Field Programmable Gate Array (FPGA) device. A simple I/O tile based circular input buffer is employed to oscillate the input signal periodically, and then a multi-phase TDC based on ISERDES core with a 625 ps bin size is used to accomplish the multiple measurements for getting higher resolution performance. In this paper, the design concept, architecture, as well as kernel implementation considerations are all discussed. To evaluate the TDC's performance, we built a verification system based on Kintex-7 FPGA. Initial test results indicate that the TDC's effective bin size is successfully reduced from 625 ps to 78.125 ps, and the measured dual-channel time resolution is better than 35 ps RMS.