P4-CoDel: Experiences on Programmable Data Plane Hardware
Ralf Kundel, Amr Rizk, Jeremias Blendin, Boris Koldehofe, Rhaban Hark,, Ralf Steinmetz

TL;DR
This paper explores implementing the CoDel Active Queue Management algorithm on programmable P4 data plane hardware, addressing challenges, demonstrating feasibility, and providing open-source code and measurements.
Contribution
It presents techniques for deploying AQM algorithms like CoDel on high-speed P4-programmable hardware, which was previously challenging.
Findings
Feasibility of implementing CoDel on P4 hardware
Latency performance measurements across different hardware targets
Open source implementation and reproducibility instructions
Abstract
Fixed buffer sizing in computer networks, especially the Internet, is a compromise between latency and bandwidth. A decision in favor of high bandwidth, implying larger buffers, subordinates the latency as a consequence of constantly filled buffers. This phenomenon is called Bufferbloat. Active Queue Management (AQM) algorithms such as CoDel or PIE, designed for the use on software based hosts, offer a flow agnostic remedy to Bufferbloat by controlling the queue filling and hence the latency through subtle packet drops. In previous work, we have shown that the data plane programming language P4 is powerful enough to implement the CoDel algorithm. While legacy software algorithms can be easily compiled onto almost any processing architecture, this is not generally true for AQM on programmable data plane hardware, i.e., programmable packet processors. In this work, we highlight…
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