A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era
Siyuan Niu (LIRMM), Adrien Suau (LIRMM, CERFACS), Gabriel Staffelbach, (CERFACS), Aida Todri-Sanial (LIRMM, CNRS)

TL;DR
This paper introduces a hardware-aware heuristic algorithm for qubit mapping in NISQ quantum computers, improving circuit fidelity and reducing additional gates by considering hardware calibration data during compilation.
Contribution
The proposed HA algorithm is the first to incorporate hardware calibration data into qubit mapping, enhancing fidelity and efficiency over existing methods.
Findings
Outperforms state-of-the-art in circuit fidelity
Reduces the number of additional gates needed
Effective on IBM quantum hardware
Abstract
Due to several physical limitations in the realisation of quantum hardware, today's quantum computers are qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realisations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbour connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this paper, we propose a Hardware-Aware mapping transition algorithm (HA) that takes the calibration data into account with…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Parallel Computing and Optimization Techniques · Quantum Information and Cryptography
