Resonant Energy Recycling SRAM Architecture

TL;DR

This paper introduces a resonant energy recovery SRAM architecture that significantly reduces dynamic power consumption by up to 30% at 1GHz, using a novel series resonance scheme and supply boosting techniques.

Contribution

It presents the first series resonance scheme for SRAM, demonstrating substantial power savings through SPICE simulations and test chip validation in 28nm CMOS technology.

Findings

Up to 30% dynamic power savings at 1GHz

Successful implementation in 144KB SRAM cache

Validated through SPICE and test chip experiments

Abstract

Although we may be at the end of Moore's law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.