Exploring the acceleration of the Met Office NERC Cloud model using FPGAs

TL;DR

This paper explores porting a key atmospheric modeling kernel to FPGAs using HLS, demonstrating performance considerations and challenges compared to traditional CPU implementations in HPC environments.

Contribution

It presents a detailed case study of adapting a complex atmospheric model kernel for FPGA acceleration, highlighting the process, challenges, and performance insights.

Findings

FPGA porting can significantly impact kernel performance.

Adapting algorithms to data-flow architecture is crucial for FPGA efficiency.

FPGAs show potential but have fundamental limits in HPC acceleration.

Abstract

The use of Field Programmable Gate Arrays (FPGAs) to accelerate computational kernels has the potential to be of great benefit to scientific codes and the HPC community in general. With the recent developments in FPGA programming technology, the ability to port kernels is becoming far more accessible. However, to gain reasonable performance from this technology it is not enough to simple transfer a code onto the FPGA, instead the algorithm must be rethought and recast in a data-flow style to suit the target architecture. In this paper we describe the porting, via HLS, of one of the most computationally intensive kernels of the Met Office NERC Cloud model (MONC), an atmospheric model used by climate and weather researchers, onto an FPGA. We describe in detail the steps taken to adapt the algorithm to make it suitable for the architecture and the impact this has on kernel performance. Using a PCIe mounted FPGA with on-board DRAM, we consider the integration on this kernel within a larger infrastructure and explore the performance characteristics of our approach in contrast to Intel CPUs that are popular in modern HPC machines, over problem sizes involving very large grids. The result of this work is an experience report detailing the challenges faced and lessons learnt in porting this complex computational kernel to FPGAs, as well as exploring the role that FPGAs can play and their fundamental limits in accelerating traditional HPC workloads.