Weighing up the new kid on the block: Impressions of using Vitis for HPC software development

TL;DR

This paper evaluates Xilinx's Vitis platform for FPGA-based HPC development, highlighting its improvements in accessibility but emphasizing the continued need for algorithmic understanding for optimal performance.

Contribution

The study provides an in-depth exploration of Vitis for HPC, demonstrating its benefits and limitations in making FPGA programming more accessible for software developers.

Findings

Vitis significantly lowers the barrier to FPGA programming in HPC.

Understanding dataflow algorithms remains crucial for performance optimization.

Vitis is not a complete solution; expertise in architecture still benefits developers.

Abstract

The use of reconfigurable computing, and FPGAs in particular, has strong potential in the field of High Performance Computing (HPC). However the traditionally high barrier to entry when it comes to programming this technology has, until now, precluded widespread adoption. To popularise reconfigurable computing with communities such as HPC, Xilinx have recently released the first version of Vitis, a platform aimed at making the programming of FPGAs much more a question of software development rather than hardware design. However a key question is how well this technology fulfils the aim, and whether the tooling is mature enough such that software developers using FPGAs to accelerate their codes is now a more realistic proposition, or whether it simply increases the convenience for existing experts. To examine this question we use the Himeno benchmark as a vehicle for exploring the Vitis platform for building, executing and optimising HPC codes, describing the different steps and potential pitfalls of the technology. The outcome of this exploration is a demonstration that, whilst Vitis is an excellent step forwards and significantly lowers the barrier to entry in developing codes for FPGAs, it is not a silver bullet and an underlying understanding of dataflow style algorithmic design and appreciation of the architecture is still key to obtaining good performance on reconfigurable architectures.