A general approach for identifying hierarchical symmetry constraints for analog circuit layout

TL;DR

This paper introduces a hierarchical, graph-based method utilizing neural networks to automatically identify complex symmetry constraints in analog circuit layouts, enhancing automation and versatility.

Contribution

It presents a novel hierarchical, graph-based algorithm with neural network support for identifying diverse symmetry constraints in circuit layout synthesis.

Findings

Effective in identifying multiple axes of symmetry

Capable of detecting approximate repeated structures

Demonstrated on various circuit types

Abstract

Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile algorithm, applicable to a broad variety of circuits, has been elusive. This paper presents a general methodology for the automated generation of symmetry constraints, and applies these constraints to guide automated layout synthesis. While prior approaches were restricted to identifying simple symmetries, the proposed method operates hierarchically and uses graph-based algorithms to extract multiple axes of symmetry within a circuit. An important ingredient of the algorithm is its ability to identify arrays of repeated structures. In some circuits, the repeated structures are not perfect replicas and can only be found through approximate graph matching. A fast graph neural network based methodology is developed for this purpose, based on evaluating the graph edit distance. The utility of this algorithm is demonstrated on a variety of circuits, including operational amplifiers, data converters, equalizers, and low-noise amplifiers.