System measurement of Intel AEP Optane DIMM

TL;DR

This paper measures and analyzes the performance and architecture of Intel AEP Optane DIMM, revealing key parameters and design features crucial for advancing non-volatile memory system research.

Contribution

It provides the first detailed measurements of AEP DIMM's performance and architecture, including cache design parameters, aiding future NVMM optimization efforts.

Findings

Estimated write latency of AEP DIMM.

Discovered DRAM cache tag organization and cache associativity.

Published new architectural insights for AEP DIMM.

Abstract

In recent years, memory wall has been a great performance bottleneck of computer system. To overcome it, Non-Volatile Main Memory (NVMM) technology has been discussed widely to provide a much larger main memory capacity. Last year, Intel released AEP Optane DIMM, which provides hundreds of GB capacity as a promising replacement of traditional DRAM memory. But as most key parameters of AEP is not open to users, there is a need to get to know them because they will guide a direction of further NVMM research. In this paper, we focus on measuring performance and architecture features of AEP DIMM. Together, we explore the design of DRAM cache which is an important part of DRAM-AEP hybrid memory system. As a result, we estimate the write latency of AEP DIMM which has not been measured accurately. And, we discover the current design parameters of DRAM cache, such as tag organization, cache associativity and set index mapping. All of these features are first published on academic paper which are greatly helpful to future NVMM optimizations.