Performance Modeling of Streaming Kernels and Sparse Matrix-Vector Multiplication on A64FX

TL;DR

This paper develops and validates an ECM performance model for the A64FX CPU, providing insights and optimization strategies for streaming kernels and sparse matrix-vector multiplication, highlighting architectural peculiarities and effective data formats.

Contribution

It constructs and validates an ECM performance model for A64FX, offering new optimization insights and recommendations for SpMV and streaming kernels on this architecture.

Findings

ECM model accurately predicts A64FX performance

SELL-C-sigma format outperforms CRS for SpMV

Optimization hints improve bandwidth utilization

Abstract

The A64FX CPU powers the current number one supercomputer on the Top500 list. Although it is a traditional cache-based multicore processor, its peak performance and memory bandwidth rival accelerator devices. Generating efficient code for such a new architecture requires a good understanding of its performance features. Using these features, we construct the Execution-Cache-Memory (ECM) performance model for the A64FX processor in the FX700 supercomputer and validate it using streaming loops. We also identify architectural peculiarities and derive optimization hints. Applying the ECM model to sparse matrix-vector multiplication (SpMV), we motivate why the CRS matrix storage format is inappropriate and how the SELL-C-sigma format with suitable code optimizations can achieve bandwidth saturation for SpMV.