Reliability-Performance Trade-offs in Neuromorphic Computing

TL;DR

This paper investigates the reliability-performance trade-offs in neuromorphic computing architectures with NVM crossbars, highlighting how parasitic voltage drops affect programming speed and endurance, and demonstrating how SNN mapping can exploit these trade-offs.

Contribution

It reveals the impact of parasitic voltage drops on NVM cell reliability and performance, and shows how SNN mapping techniques can leverage these effects for optimization.

Findings

Shorter current paths lead to faster programming but lower endurance.

Longer current paths have higher endurance but slower programming.

SNN mapping can exploit voltage drop asymmetries for improved reliability-performance balance.

Abstract

Neuromorphic architectures built with Non-Volatile Memory (NVM) can significantly improve the energy efficiency of machine learning tasks designed with Spiking Neural Networks (SNNs). A major source of voltage drop in a crossbar of these architectures are the parasitic components on the crossbar's bitlines and wordlines, which are deliberately made longer to achieve lower cost-per-bit. We observe that the parasitic voltage drops create a significant asymmetry in programming speed and reliability of NVM cells in a crossbar. Specifically, NVM cells that are on shorter current paths are faster to program but have lower endurance than those on longer current paths, and vice versa. This asymmetry in neuromorphic architectures create reliability-performance trade-offs, which can be exploited efficiently using SNN mapping techniques. In this work, we demonstrate such trade-offs using a previously-proposed SNN mapping technique with 10 workloads from contemporary machine learning tasks for a state-of-the art neuromoorphic hardware.