Particle Mesh Ewald for Molecular Dynamics in OpenCL on an FPGA Cluster

TL;DR

This paper introduces a scalable, FPGA-based Particle Mesh Ewald algorithm for molecular dynamics, achieving high performance and scalability surpassing GPU implementations, suitable for large-scale drug discovery simulations.

Contribution

First fully integrated FPGA implementation of PME algorithm with OpenCL, enabling scalable, high-performance electrostatic calculations for MD simulations.

Findings

Achieved 206 microseconds per timestep on 4 FPGAs for 65536 atoms.

Outperformed GPU-based PME implementations in experimental tests.

Predicted 6.6 microseconds per timestep on 64 FPGAs.

Abstract

Molecular Dynamics (MD) simulations play a central role in physics-driven drug discovery. MD applications often use the Particle Mesh Ewald (PME) algorithm to accelerate electrostatic force computations, but efficient parallelization has proven difficult due to the high communication requirements of distributed 3D FFTs. In this paper, we present the design and implementation of a scalable PME algorithm that runs on a cluster of Intel Stratix 10 FPGAs and can handle FFT sizes appropriate to address real-world drug discovery projects (grids up to $128^3$). To our knowledge, this is the first work to fully integrate all aspects of the PME algorithm (charge spreading, 3D FFT/IFFT, and force interpolation) within a distributed FPGA framework. The design is fully implemented with OpenCL for flexibility and ease of development and uses 100 Gbps links for direct FPGA-to-FPGA communications without the need for host interaction. We present experimental data up to 4 FPGAs (e.g., 206 microseconds per timestep for a 65536 atom simulation and $64^3$ 3D FFT), outperforming GPUs. Additionally, we discuss design scalability on clusters with differing topologies up to 64 FPGAs (with expected performance greater than all known GPU implementations) and integration with other hardware components to form a complete molecular dynamics application. We predict best-case performance of 6.6 microseconds per timestep on 64 FPGAs.