The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing

TL;DR

This paper proposes a comprehensive dataflow architecture for future supercomputers-on-a-chip, integrating multiple processing units and accelerators to optimize scientific computing, geophysics, complex mathematics, and information processing tasks.

Contribution

It introduces a novel dataflow design combining big multi-core, many-core processors, and specialized accelerators tailored for diverse high-performance computing applications.

Findings

Enhanced computational efficiency for scientific applications

Optimized data movement and processing in integrated architectures

Potential for scalable supercomputing-on-a-chip solutions

Abstract

This article starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used Machine Learning algorithms needed in bandwidth-bound applications and a flexible-structure reprogrammable accelerator for less frequently used Machine Learning algorithms needed in latency-critical applications.