A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA

TL;DR

This paper presents a reduced-precision FPGA architecture for sparse matrix-vector multiplication tailored for Personalized PageRank, achieving significant speedups and energy efficiency improvements over CPU implementations.

Contribution

A novel streaming COO sparse matrix-vector multiplication architecture on FPGA that enhances performance and energy efficiency for Personalized PageRank.

Findings

Up to 6x speedup over floating-point FPGA implementation.

Up to 42x higher energy efficiency compared to CPU.

Effective preservation of numerical fidelity.

Abstract

Sparse matrix-vector multiplication is often employed in many data-analytic workloads in which low latency and high throughput are more valuable than exact numerical convergence. FPGAs provide quick execution times while offering precise control over the accuracy of the results thanks to reduced-precision fixed-point arithmetic. In this work, we propose a novel streaming implementation of Coordinate Format (COO) sparse matrix-vector multiplication, and study its effectiveness when applied to the Personalized PageRank algorithm, a common building block of recommender systems in e-commerce websites and social networks. Our implementation achieves speedups up to 6x over a reference floating-point FPGA architecture and a state-of-the-art multi-threaded CPU implementation on 8 different data-sets, while preserving the numerical fidelity of the results and reaching up to 42x higher energy efficiency compared to the CPU implementation.