Modeling Techniques for Logic Locking

TL;DR

This paper introduces two SAT modeling techniques, relaxed encodings and symmetry breaking, which significantly accelerate the process of breaking logic locking schemes, and proposes an improved locking method resistant to these techniques.

Contribution

The paper presents novel SAT modeling techniques that drastically speed up attacks on logic locking and proposes a new locking scheme resistant to these methods.

Findings

Relaxed encodings and symmetry breaking speed up SAT attacks by many orders of magnitude.

State-of-the-art locking can be broken in seconds using these techniques.

Logic-enhanced Banyan locking resists the proposed modeling attacks.

Abstract

Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.