Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator

TL;DR

This paper presents an open-source, HDL-described 20 GS/s 8-bit ADC and a 5-GHz phase interpolator, designed with digital standard cells for high-speed serial links, emphasizing portability and minimal design effort.

Contribution

It introduces a fully HDL-described, synthesizable analog block design approach for high-speed ADCs and phase interpolators, enabling easy porting and open sharing.

Findings

Achieved 20 GS/s sampling rate with 5.6 ENOB

Designed with digital standard cells for process portability

Power dissipation of 175 mW in 0.102 mm2 area

Abstract

Using digital standard cells and digital place-and-route (PnR) tools, we created a 20 GS/s, 8-bit analog-to-digital converter (ADC) for use in high-speed serial link applications with an ENOB of 5.6, a DNL of 0.96 LSB, and an INL of 2.39 LSB, which dissipated 175 mW in 0.102 mm2 in a 16nm technology. The design is entirely described by HDL so that it can be ported to other processes with minimal effort and shared as open source.