SideLine: How Delay-Lines (May) Leak Secrets from your SoC
Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet, Moundi

TL;DR
This paper introduces SideLine, a novel side-channel attack exploiting delay-line components in high-end SoCs to remotely extract cryptographic secrets, demonstrating practical attacks across different vendors and operating system environments.
Contribution
The work presents a new side-channel vector using delay-line components in SoCs and provides a detailed method to perform remote power side-channel attacks exploiting this vector.
Findings
Successfully recovered AES keys from victim processes across different cores.
Demonstrated attack feasibility on multiple SoC vendors.
Attacks remain effective even with OS-level process isolation.
Abstract
To meet the ever-growing need for performance in silicon devices, SoC providers have been increasingly relying on software-hardware cooperation. By controlling hardware resources such as power or clock management from the software, developers earn the possibility to build more flexible and power efficient applications. Despite the benefits, these hardware components are now exposed to software code and can potentially be misused as open-doors to jeopardize trusted environments, perform privilege escalation or steal cryptographic secrets. In this work, we introduce SideLine, a novel side-channel vector based on delay-line components widely implemented in high-end SoCs. After providing a detailed method on how to access and convert delay-line data into power consumption information, we demonstrate that these entities can be used to perform remote power side-channel attacks. We report…
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