A Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout

TL;DR

This paper introduces two low-power, low-latency dual-channel serializer ASICs, LOCx2 and LOCx2-130, designed for detector front-end readout, demonstrating high data rates and efficient power consumption in different CMOS processes.

Contribution

The paper presents a novel dual-channel serializer ASIC with high data rates and low latency, fabricated in two different CMOS processes for detector readout applications.

Findings

LOCx2 operates at 5.12 Gbps with 900 mW power and 27 ns latency.

LOCx2-130 operates at 4.8 Gbps with 386 mW power and 38 ns latency.

Both ASICs are pin-compatible and suitable for detector front-end readout.

Abstract

In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.