MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs

TL;DR

This paper introduces MERAM, a non-volatile cache memory based on Magneto-Electric FETs, demonstrating significant energy, area, and latency improvements over traditional SRAM and other non-volatile memories through a comprehensive device-to-architecture evaluation.

Contribution

It proposes the first non-volatile 2T-1MEFET memory cell with separate read/write paths and develops a cross-layer evaluation framework for benchmarking MERAM against existing memory technologies.

Findings

MERAM exhibits 36x sense current difference for high state distinguishability.

It reduces EAT product by ~98% compared to 6T SRAM.

It outperforms 2T SOT-MRAM in energy, area, and latency metrics.

Abstract

Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers intriguing characteristics for high speed and low-power design in both logic and memory applications. In this paper, for the first time, we propose a non-volatile 2T-1MEFET memory bit-cell with separate read and write paths. We show that with proper co-design at the device, cell and array levels, such a design is a promising candidate for fast non-volatile cache memory, termed as MERAM. To further evaluate its performance in memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework based on an experimentally-calibrated MEFET device model to quantitatively analyze and benchmark the proposed MERAM design with other memory technologies, including both volatile memory (i.e. SRAM, eDRAM) and other popular non-volatile emerging memory (i.e. ReRAM, STT-MRAM, and SOT-MRAM). The experiment results show that MERAM has a high state distinguishability with almost 36x magnitude difference in sense current. Results for the PARSEC benchmark suite indicate that as an L2 cache alternative, MERAM reduces Energy Area Latency (EAT) product on average by ~98\% and ~70\% compared with typical 6T SRAM and 2T SOT-MRAM platforms, respectively.