Fast LDPC GPU Decoder for Cloud RAN

TL;DR

This paper presents a GPU-based decoder for 5G NR LDPC codes that achieves higher throughput than FPGA implementations, emphasizing flexibility and rapid deployment for cloud RAN applications.

Contribution

A novel GPU decoder design for 5G NR LDPC codes that improves throughput and resource utilization over previous layered designs and FPGA implementations.

Findings

GPU decoder has 3X higher throughput than FPGA-based decoder.

GPU decoder achieves 3 to 5X lower decoding power efficiency.

Design is adaptable to GPU architecture for high resource utilization.

Abstract

The GPU as a digital signal processing accelerator for cloud RAN is investigated. A new design for a 5G NR low density parity check code decoder running on a GPU is presented. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves over an existing layered design that processes additional codewords in parallel to increase utilization. In comparison to a decoder implemented on a FPGA (757K gate), the new GPU (24 core) decoder has 3X higher throughput. The GPU decoder exhibits 3 to 5X lower decoding power efficiency, as typical of a general-purpose processor. Thus, GPUs may find application as cloud accelerators where rapid deployment and flexibility are prioritized over decoding power efficiency.