Deep Learning Interference Cancellation in Wireless Networks

TL;DR

This paper introduces a neural network-based interference cancellation method for wireless networks that enhances data reliability without feedback, suitable for low-latency, high-rate applications, and demonstrates significant SER improvements.

Contribution

It presents a novel deep learning approach for physical layer interference cancellation integrated with traditional DSP, advancing wireless communication reliability.

Findings

Significant reduction in symbol error rate (SER) with the proposed method.

Effective real-time interference cancellation compatible with existing systems.

Feasibility of hardware implementation considering latency and power constraints.

Abstract

With the crowding of the electromagnetic spectrum and the shrinking cell size in wireless networks, crosstalk between base stations and users is a major problem. Although hand-crafted functional blocks and coding schemes are proven effective to guarantee reliable data transfer, currently deep learning-based approaches have drawn increasing attention in the communication system modeling. In this paper, we propose a Neural Network (NN) based signal processing technique that works with traditional DSP algorithms to overcome the interference problem in realtime. This technique doesn't require any feedback protocol between the receiver and transmitter which makes it very suitable for low-latency and high data-rate applications such as autonomy and augmented reality. While there has been recent work on the use of Reinforcement Learning (RL) in the control layer to manage and control the interference, our approach is novel in the sense that it introduces a neural network for signal processing at baseband data rate and in the physical layer. We demonstrate this "Deep Interference Cancellation" technique using a convolutional LSTM autoencoder. When applied to QAM-OFDM modulated data, the network produces significant improvement in the symbol error rate (SER). We further discuss the hardware implementation including latency, power consumption, memory requirements, and chip area.