HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment
Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard

TL;DR
HECTOR-V introduces a heterogeneous CPU architecture with an embedded security-hardened RISC-V processor to enhance TEE security, isolation, and secure communication, addressing limitations of traditional TEEs.
Contribution
The paper presents a novel heterogeneous architecture with an embedded RISC-V secure co-processor that improves TEE security, isolation, and communication capabilities.
Findings
Strong isolation between secure and non-secure domains achieved
Secure communication channels established effectively
Enhanced security features like control-flow integrity implemented
Abstract
To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these approaches only cover a narrow threat model resulting in limited security guarantees. Enclaves in the application processor typically provide weak isolation between the secure and non-secure domain, especially when considering side-channel attacks. Although secure elements do provide strong isolation, the slow communication interface to the application processor is exposed to adversaries and restricts the use cases. Independently of the used implementation approach, TEEs often lack the possibility to…
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