A 6.3-Nanowatt-per-Channel 96-Channel Neural Spike Processor for a Movement-Intention-Decoding Brain-Computer-Interface Implant

TL;DR

This paper introduces a highly energy-efficient neural spike processing hardware for brain-computer interfaces, capable of real-time movement decoding with minimal power consumption and high integration.

Contribution

It presents a novel low-power, high-integration neural signal processing chip with algorithms optimized for accuracy and efficiency in movement-intention decoding.

Findings

Achieved 0.61 μW power dissipation for 96 channels

Reduced wireless data rate by over four orders of magnitude

Matched or surpassed state-of-the-art decoding accuracy

Abstract

This paper presents microwatt end-to-end neural signal processing hardware for deployment-stage real-time upper-limb movement intent decoding. This module features intercellular spike detection, sorting, and decoding operations for a 96-channel prosthetic implant. We design the algorithms for those operations to achieve minimal computation complexity while matching or advancing the accuracy of state-of-art Brain-Computer-Interface sorting and movement decoding. Based on those algorithms, we devise the architect of the neural signal processing hardware with the focus on hardware reuse and event-driven operation. The design achieves among the highest levels of integration, reducing wireless data rate by more than four orders of magnitude. The chip prototype in a 180-nm high-VTH, achieving the lowest power dissipation of 0.61 uW for 96 channels, 21X lower than the prior art at a comparable/better accuracy even with integration of kinematic state estimation computation.