Massive Machine Type Communication Pilot-Hopping Sequence Detection Architectures Based on Non-Negative Least Squares for Grant-Free Random Access
Narges Mohammadi Sarband, Ema Becirovic, Mattias Krysander, Erik G., Larsson, Oscar Gustafsson

TL;DR
This paper proposes two parallel architectures based on NNLS algorithms for user activity detection in grant-free mMTC, achieving high detection rates with low power and small chip area.
Contribution
It introduces two novel parallel NNLS-based detection architectures optimized for low power and high speed in grant-free mMTC.
Findings
Fast projected gradient algorithm converges quickly with about 0.7 mm² chip area.
Multiplicative updates algorithm has smaller chip area (~0.5 mm²) and lower power consumption.
Detection rate of about one million detections per second achieved with low energy per detection.
Abstract
User activity detection in grant-free random access massive machine type communication (mMTC) using pilot-hopping sequences can be formulated as solving a non-negative least squares (NNLS) problem. In this work, two architectures using different algorithms to solve the NNLS problem is proposed. The algorithms are implemented using a fully parallel approach and fixed-point arithmetic, leading to high detection rates and low power consumption. The first algorithm, fast projected gradients, converges faster to the optimal value. The second algorithm, multiplicative updates, is partially implemented in the logarithmic domain, and provides a smaller chip area and lower power consumption. For a detection rate of about one million detections per second, the chip area for the fast algorithm is about 0.7 mm compared to about 0.5 mm for the multiplicative algorithm when implemented in a…
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