Agile SoC Development with Open ESP

TL;DR

The paper presents ESP, an open-source, modular platform for agile heterogeneous SoC development that integrates automated design flows for accelerators and system prototyping on FPGA, supporting both software and hardware engineers.

Contribution

It introduces ESP, a scalable, open-source platform combining modular architecture and automated flows for heterogeneous SoC design and prototyping.

Findings

Supports agile SoC development through automation and modularity.

Enables system-level design and FPGA prototyping.

Facilitates integration of accelerators for software and hardware engineers.

Abstract

ESP is an open-source research platform for heterogeneous SoC design. The platform combines a modular tile-based architecture with a variety of application-oriented flows for the design and optimization of accelerators. The ESP architecture is highly scalable and strikes a balance between regularity and specialization. The companion methodology raises the level of abstraction to system-level design and enables an automated flow from software and hardware development to full-system prototyping on FPGA. For application developers, ESP offers domain-specific automated solutions to synthesize new accelerators for their software and to map complex workloads onto the SoC architecture. For hardware engineers, ESP offers automated solutions to integrate their accelerator designs into the complete SoC. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP supports the open-source hardware community by providing a flexible platform for agile SoC development.