DAVE: Deriving Automatically Verilog from English

TL;DR

This paper presents DAVE, a machine learning approach that fine-tunes GPT-2 to automatically translate English specifications into Verilog code, simplifying digital system design for engineers.

Contribution

It introduces a novel dataset and demonstrates effective translation of natural language to Verilog using GPT-2, achieving high accuracy on novice-level tasks.

Findings

94.8% correct translation accuracy

Effective handling of simple and abstract design tasks

Feasibility of using fine-tuned GPT-2 for digital design automation

Abstract

While specifications for digital systems are provided in natural language, engineers undertake significant efforts to translate them into the programming languages understood by compilers for digital systems. Automating this process allows designers to work with the language in which they are most comfortable --the original natural language -- and focus instead on other downstream design challenges. We explore the use of state-of-the-art machine learning (ML) to automatically derive Verilog snippets from English via fine-tuning GPT-2, a natural language ML system. We describe our approach for producing a suitable dataset of novice-level digital design tasks and provide a detailed exploration of GPT-2, finding encouraging translation performance across our task sets (94.8% correct), with the ability to handle both simple and abstract design tasks.