Building Application-Specific Overlays on FPGAs with High-Level Customizable IPs
Hongbo Rong

TL;DR
This paper introduces a high-level language and compiler framework that enables software programmers to quickly create application-specific FPGA overlays with customizable IPs, improving performance and ease of use.
Contribution
It presents a novel high-level specification language and compiler that automate the creation of efficient FPGA overlays, reducing complexity compared to traditional RTL design.
Findings
Language features for overlay composition demonstrated with LU decomposer.
System under construction to support workloads like CNN.
Compiler automates optimization and scheduling for overlays.
Abstract
Overlays are virtual, re-configurable architectures that overlay on top of physical FPGA fabrics. An overlay that is specialized for an application, or a class of applications, offers both fast reconfiguration and minimized performance penalty. Such an overlay is usually implemented by hardware designers in hardware "assembly" languages at register-transfer level (RTL). This short article proposes an idea for a software programmer, instead of hardware designers, to quickly implement an application-specific overlay using high-level customizable IPs. These IPs are expressed succinctly by a specification language, whose abstraction level is much higher than RTL but can nonetheless expresses many performance-critical loop and data optimizations on FPGAs, and thus would offer competitively high performance at a much lower cost of maintenance and much easier customizations. We propose new…
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and Analog Circuit Testing · Interconnection Networks and Systems
