RISC micrprocessor verification

TL;DR

This paper discusses the challenges and methods of verifying complex RISC microprocessors, focusing on the ARM Cortex M3, through concurrent functional verification during design implementation.

Contribution

It presents an approach to verify a complex ARM Cortex M3 processor, addressing verification challenges in modern pipelined RISC microprocessors.

Findings

Verification was performed concurrently with design implementation.

Focus on verifying caches, pipeline, ALUs, and bypass logic.

Ensured the processor fulfills all abstract assertions.

Abstract

Today's microprocessors have grown significantly in complexity and functionality. Most of today's processors provide at least three levels of memory hierarchy, are heavily pipelined, and support some sort of cache coherency protocol. These features are extremely complex and sophisticated, and present their own set of unique verification challenges. Verification is clearly not a point tool, but is part of a process that starts from initial product conception and is to some degrees complete when the product goes to market. Functional verification is necessary to verify the functionality at RTL level. Complex micro-processors like ARM are high performance, low cost and low power 32-bit RISC processors. In our paper complex microprocessor is ARM cortex M3, developed for the embedded applications having low interrupt latency, low gate count, 3- stage pipelining, branch prediction, THUMB and THUMB-2 instruction set. Functional verification is used to verify that the circuit full fills each abstract assertion under the implementation mapping. we explore several aspects of processor design, including caches, pipeline depth, ALUs, and bypass logic.The verification was done concurrently with the design implementation of the processor.