Machine learning thermal circuit network model for thermal design optimization of electronic circuit board layout with transient heating chips

TL;DR

This paper presents a combined Bayesian optimization and thermal circuit network model to efficiently optimize electronic circuit board layouts with transient heating, significantly reducing computational time compared to traditional methods.

Contribution

It introduces a novel integration of Bayesian optimization with a lamped-capacitance thermal circuit model for faster thermal design optimization of electronic boards.

Findings

BO found optimal layouts in about 7 minutes from 10 million patterns.

BO reduced CPU time to 1/5 and 1/4 of PSO and GA respectively.

BO identified non-intuitive solutions efficiently.

Abstract

This paper describes a method combining Bayesian optimization (BO) and a lamped-capacitance thermal circuit network model that is effective for speeding up the thermal design optimization of an electronic circuit board layout with transient heating chips. As electronic devices have become smaller and more complex, the importance of thermal design optimization to ensure heat dissipation performance has increased. However, such thermal design optimization is difficult because it is necessary to consider various trade-offs associated with packaging and transient temperature changes of heat-generating components. This study aims to improve the performance of thermal design optimization by artificial intelligence. BO using a Gaussian process was combined with the lamped-capacitance thermal circuit network model, and its performance was verified by case studies. As a result, BO successfully found the ideal circuit board layout as well as particle swarm optimization (PSO) and genetic algorithm (GA) could. The CPU time for BO was 1/5 and 1/4 of that for PSO and GA, respectively. In addition, BO found a non-intuitive optimal solution in approximately 7 minutes from 10 million layout patterns. It was estimated that this was 1/1000 of the CPU time required for analyzing all layout patterns.