Multi-frequency Data Parallel Spin Wave Logic Gates

TL;DR

This paper introduces a novel multi-frequency spin wave computing approach enabling parallel data processing, demonstrating optimized 8-bit gates with significant area reduction and discussing practical parallelism limits through simulations.

Contribution

It proposes a multi-frequency spin wave logic architecture, implements byte-wide gates, and introduces an optimization algorithm to reduce area overhead, advancing spin wave computing capabilities.

Findings

Byte-wide XOR and Majority gates are validated via simulations.

Optimization reduces gate area by up to 41%.

Parallelism can be increased to 16 with threshold detection.

Abstract

By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide without affecting each other, while only interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing. In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates.