Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

TL;DR

This paper proposes using monolithic 3D integration to reorganize DRAM cell-arrays, effectively reducing latency, power, and area costs, thus addressing fundamental tradeoffs in DRAM design.

Contribution

It introduces a novel DRAM cell-array organization using M3D technology to mitigate latency-area tradeoffs, demonstrating significant improvements over conventional designs.

Findings

Up to 9.56% latency reduction

Up to 4.96% power savings

Up to 21.21% energy-delay product reduction

Abstract

Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access path. However, doing so decreases DRAM area-efficiency, exacerbating the latency-area tradeoffs for DRAM design. In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can mitigate these fundamental latency-area tradeoffs. Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency, up to 4.96% less power consumption, and up to 21.21% less energy-delay product (EDP), with up to 14% less DRAM die area, com-pared to the conventional 2D DDR4 DRAM.