LC-NAS: Latency Constrained Neural Architecture Search for Point Cloud Networks

TL;DR

LC-NAS introduces a latency-constrained neural architecture search framework for point cloud networks, enabling the design of efficient models that meet specific latency targets without significant accuracy loss, suitable for hardware-limited applications.

Contribution

The paper proposes a novel latency constraint formulation in NAS for point cloud networks, guaranteeing latency bounds and enabling targeted latency-accuracy trade-offs.

Findings

Achieves state-of-the-art accuracy on ModelNet40 classification.

Successfully transfers architectures to part segmentation with reduced latency.

Maintains performance with minimal computational cost during search.

Abstract

Point cloud architecture design has become a crucial problem for 3D deep learning. Several efforts exist to manually design architectures with high accuracy in point cloud tasks such as classification, segmentation, and detection. Recent progress in automatic Neural Architecture Search (NAS) minimizes the human effort in network design and optimizes high performing architectures. However, these efforts fail to consider important factors such as latency during inference. Latency is of high importance in time critical applications like self-driving cars, robot navigation, and mobile applications, that are generally bound by the available hardware. In this paper, we introduce a new NAS framework, dubbed LC-NAS, where we search for point cloud architectures that are constrained to a target latency. We implement a novel latency constraint formulation to trade-off between accuracy and latency in our architecture search. Contrary to previous works, our latency loss guarantees that the final network achieves latency under a specified target value. This is crucial when the end task is to be deployed in a limited hardware setting. Extensive experiments show that LC-NAS is able to find state-of-the-art architectures for point cloud classification in ModelNet40 with minimal computational cost. We also show how our searched architectures achieve any desired latency with a reasonably low drop in accuracy. Finally, we show how our searched architectures easily transfer to a different task, part segmentation on PartNet, where we achieve state-of-the-art results while lowering latency by a factor of 10.