Low-complexity Architecture for AR(1) Inference

TL;DR

This paper introduces a low-complexity estimator for AR(1) correlation inference that is hardware-efficient, maintaining accuracy while significantly reducing power consumption and increasing operational speed.

Contribution

A novel low-complexity estimator for AR(1) correlation that is suitable for low-power hardware implementation, with comparable accuracy to existing methods.

Findings

Performs comparably to existing methods with maximum error around 10^{-2}

Reduces dynamic power consumption by over 95% in hardware

Doubles maximum operating frequency in hardware implementations

Abstract

In this Letter, we propose a low-complexity estimator for the correlation coefficient based on the signed $\operatorname{AR}(1)$ process. The introduced approximation is suitable for implementation in low-power hardware architectures. Monte Carlo simulations reveal that the proposed estimator performs comparably to the competing methods in literature with maximum error in order of $10^{-2}$. However, the hardware implementation of the introduced method presents considerable advantages in several relevant metrics, offering more than 95% reduction in dynamic power and doubling the maximum operating frequency when compared to the reference method.