High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

TL;DR

This paper introduces ENEAC, a methodology for heterogeneous computing on SoCs that combines CPU and FPGA accelerators with a scheduler, significantly boosting performance and efficiency for irregular workloads.

Contribution

The paper presents ENEAC, a novel heterogeneous scheduling approach that enables efficient CPU-FPGA collaboration on SoCs using existing tools and unified programming.

Findings

Up to 17% performance improvement with all resources.

Up to 865% performance increase using only CPU.

Workflow simplifies development with existing tools.

Abstract

This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.