Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications

TL;DR

This paper introduces a new quasi delay insensitive (QDI) asynchronous majority voter optimized for area efficiency in TMR systems, significantly reducing area compared to existing designs for fault-tolerant applications.

Contribution

A novel QDI asynchronous majority voter is proposed, achieving 30.2% less area than previous designs, enhancing resource efficiency in TMR fault-tolerant systems.

Findings

The proposed QDI majority voter reduces area by 30.2%.

Implementation in 32/28nm CMOS process demonstrates practical viability.

Uses dual rail code and 4-phase handshake protocols for robust asynchronous communication.

Abstract

Mission-critical and safety-critical applications generally tend to incorporate triple modular redundancy (TMR) to embed fault tolerance in their physical implementations. In a TMR realization, an original function block, which may be a circuit or a system, and two exact copies of the function block are used to successfully overcome any temporary fault or permanent failure of an arbitrary function block during the routine operation. The corresponding outputs of the function blocks are majority voted using 3-input majority voters whose outputs define the outputs of a TMR realization. Hence, a 3-input majority voter forms an important component of a TMR realization. Many synchronous majority voters and an asynchronous non-delay insensitive majority voter have been presented in the literature. Recently, quasi delay insensitive (QDI) asynchronous majority voters for TMR applications were also discussed in the literature. In this regard, this paper presents a new QDI asynchronous majority voter for TMR applications, which is better optimized in area compared to the existing QDI majority voters. The proposed QDI majority voter requires 30.2% less area compared to the best of the existing QDI majority voters, and this could be useful for resource-constrained fault tolerance applications. The example QDI TMR circuits were implemented using a 32/28nm complementary metal oxide semiconductor (CMOS) process. The delay insensitive dual rail code was used for data encoding, and 4-phase return-to-zero and return-to-one handshake protocols were used for data communication.