Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision

TL;DR

This paper introduces a reconfigurable 6T SRAM-based in-memory computing architecture supporting various bit-precisions, enabling low-latency complex computations with high energy efficiency in a 28nm CMOS process.

Contribution

It proposes a novel SRAM-based IMC architecture with reconfigurable bit-precision and low-latency carry-propagation, achieving high speed and energy efficiency.

Findings

Achieves 2.25GHz at 1.0V in 28nm CMOS

Attains 0.68 TOPS/W for addition

Supports wide voltage range from 0.6V to 1.1V

Abstract

This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By performing carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 1.0V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.