Design Space Exploration of Power Delivery For Advanced Packaging Technologies

TL;DR

This paper explores various power delivery network configurations in advanced multi-chip 2.5-D and 3-D ICs, focusing on VRM placement to minimize power supply noise and comparing different design options.

Contribution

It provides a comprehensive analysis of VRM placement strategies and configurations in 2.5-D and 3-D ICs, highlighting the most effective approaches for PSN suppression.

Findings

3D chip-on-VRM configuration best suppresses PSN.

VRM-chip distance significantly affects PSN levels.

On-chip decoupling capacitor density impacts noise reduction.

Abstract

In this paper, a design space exploration of power delivery networks is performed for multi-chip 2.5-D and 3-D IC technologies. The focus of the paper is the effective placement of the voltage regulator modules (VRMs) for power supply noise (PSN) suppression. Multiple on-package VRM configurations have been analyzed and compared. Additionally, 3D IC chip-on-VRM and backside-of-the-package VRM configurations are studied. From the PSN perspective, the 3D IC chip-on-VRM case suppresses the PSN the most even with high current density hotspots. The paper also studies the impact of different parameters such as VRM-chip distance on the package, on-chip decoupling capacitor density, etc. on the PSN.