Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines
Zhe Wan, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, Vwani P., Roychowdhury

TL;DR
This paper evaluates the scalability of analog compute-in-memory architectures for deep neural networks, demonstrating that specialized training methods and representations can significantly improve accuracy despite device uncertainties.
Contribution
It introduces a simulation framework for large-scale DNNs with analog NVM CIM and proposes a Hessian-Aware SGD training algorithm with floating-point DNN representations for improved accuracy.
Findings
Analog NVM CIM causes high uncertainty in DNN inference.
High-precision trained DNNs are not resilient to analog NVM uncertainties.
The proposed methods improve DNN accuracy without hardware cost increase.
Abstract
Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNN) to improve energy efficiency. Such architectures, however, leverage charge conservation, an operation with infinite resolution, and thus are susceptible to errors. The computations in DNN realized by analog NVM thus have high uncertainty due to the device stochasticity. Several reports have demonstrated the use of analog NVM for CIM in a limited scale. It is unclear whether the uncertainties in computations will prohibit large-scale DNNs. To explore this critical issue of scalability, this paper first presents a simulation framework to evaluate the feasibility of large-scale DNNs based on CIM architecture and analog NVM. Simulation results show that DNNs trained for high-precision digital computing engines are not…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · CCD and CMOS Imaging Sensors
