SpinAPS: A High-Performance Spintronic Accelerator for Probabilistic Spiking Neural Networks

TL;DR

SpinAPS is a high-performance hardware accelerator for probabilistic spiking neural networks that uses spintronic devices and digital logic, achieving significant speed and efficiency improvements over traditional designs.

Contribution

This paper introduces SpinAPS, a novel spintronic accelerator for probabilistic SNNs that implements direct learning without conversion from ANNs, enabling faster and more efficient inference.

Findings

Achieves 4x performance improvement in GSOPS/W/mm2 over SRAM-based designs.

Reaches 75% accuracy in just 4 time steps on handwritten digit tasks.

Competitive with memristor-based DNN/SNN accelerators and GPUs.

Abstract

We discuss a high-performance and high-throughput hardware accelerator for probabilistic Spiking Neural Networks (SNNs) based on Generalized Linear Model (GLM) neurons, that uses binary STT-RAM devices as synapses and digital CMOS logic for neurons. The inference accelerator, termed "SpinAPS" for Spintronic Accelerator for Probabilistic SNNs, implements a principled direct learning rule for first-to-spike decoding without the need for conversion from pre-trained ANNs. The proposed solution is shown to achieve comparable performance with an equivalent ANN on handwritten digit and human activity recognition benchmarks. The inference engine, SpinAPS, is shown through software emulation tools to achieve 4x performance improvement in terms of GSOPS/W/mm2 when compared to an equivalent SRAM-based design. The architecture leverages probabilistic spiking neural networks that employ first-to-spike decoding rule to make inference decisions at low latencies, achieving 75% of the test performance in as few as 4 algorithmic time steps on the handwritten digit benchmark. The accelerator also exhibits competitive performance with other memristor-based DNN/SNN accelerators and state-of-the-art GPUs.