A 128-point Multi-Path SC FFT Architecture

TL;DR

This paper introduces a high-throughput, area-efficient 128-point multi-path SC FFT architecture that leverages radix-2^k algorithms and optimized processing elements to reduce chip size and power consumption.

Contribution

It proposes a novel multi-path FFT architecture based on single-path radix-2^k algorithms with optimized processing elements for improved efficiency.

Findings

Achieves 0.167 mm2 chip area at 250 MHz

Consumes only 14.81 mW power

Reduces chip area and power compared to existing designs

Abstract

This paper presents a new radix-2^k multi-path FFT architecture, named MSC FFT, which is based on a single-path radix-2 serial commutator (SC) FFT architecture. The proposed multi-path architecture has a very high hardware utilization that results in a small chip area, while providing high throughput. In addition, the adoption of radix-2^k FFT algorithms allows for simplifying the rotators even further. It is achieved by optimizing the structure of the processing element (PE). The implemented architecture is a 128-point 4-parallel multi-path SC FFT using 90 nm process. Its area and power consumption at 250 MHz are only 0.167 mm2 and 14.81 mW, respectively. Compared with existing works, the proposed design reduces significantly the chip rea and the power consumption, while providing high throughput.