Negative Capacitance Enables FinFET Scaling Beyond 3nm Node

TL;DR

This paper demonstrates that negative capacitance FinFETs can be scaled beyond the 3nm node, achieving smaller nodes with improved electrical performance and meeting industry targets, thus enabling continued device scaling.

Contribution

It provides a comprehensive TCAD-based analysis showing the potential of NC-FinFETs to scale beyond 3nm, including performance benefits and scaling limits.

Findings

NC-FinFET can be scaled to 2.1nm and 1.5nm nodes.

NC-FinFET meets IRDS Ion and Ioff targets at reduced VDD.

Negative capacitance improves subthreshold slope and other device parameters.

Abstract

A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS). In addition, for the intervening nodes, NC-FinFET can meet IRDS Ion and Ioff target at target-beating VDD. The benefits of negative capacitance (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance over Id (Gd/Id), and lower VDD. Further scaling may be achieved by improving capacitance matching between ferroelectric (FE) and dielectric (DE).