Shadow-wall lithography of ballistic superconductor-semiconductor quantum devices

TL;DR

This paper introduces a shadow-wall lithography technique for fabricating high-quality, reproducible superconductor-semiconductor quantum devices, advancing the development of topological qubits with improved interface integrity.

Contribution

It presents a novel on-chip shadow-wall fabrication method that simplifies device production and enhances interface quality for topological quantum devices.

Findings

Devices exhibit a hard induced superconducting gap.

Observation of large gate-tunable supercurrents.

Detection of zero-bias conductance peaks in magnetic fields.

Abstract

The realization of a topological qubit calls for advanced techniques to readily and reproducibly engineer induced superconductivity in semiconductor nanowires. Here, we introduce an on-chip fabrication paradigm based on shadow walls that offers substantial advances in device quality and reproducibility. It allows for the implementation of novel quantum devices and ultimately topological qubits while eliminating many fabrication steps such as lithography and etching. This is critical to preserve the integrity and homogeneity of the fragile hybrid interfaces. The approach simplifies the reproducible fabrication of devices with a hard induced superconducting gap and ballistic normal-/superconductor junctions. Large gate-tunable supercurrents and high-order multiple Andreev reflections manifest the exceptional coherence of the resulting nanowire Josephson junctions. Our approach enables, in particular, the realization of 3-terminal devices, where zero-bias conductance peaks emerge in a magnetic field concurrently at both boundaries of the one-dimensional hybrids.