Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic

TL;DR

This paper presents an analytical model for NoCs with priority arbitration under bursty traffic, achieving high accuracy and addressing limitations of previous models that assumed fair arbitration and simple traffic.

Contribution

It introduces a novel analytical performance modeling technique specifically for priority-aware NoCs under bursty traffic conditions.

Findings

Less than 10% modeling error compared to cycle-accurate simulation

Effective modeling of priority arbitration in bursty traffic scenarios

Improves accuracy over existing models assuming fair arbitration

Abstract

Networks-on-Chip (NoCs) used in commercial many-core processors typically incorporate priority arbitration. Moreover, they experience bursty traffic due to application workloads. However, most state-of-the-art NoC analytical performance analysis techniques assume fair arbitration and simple traffic models. To address these limitations, we propose an analytical modeling technique for priority-aware NoCs under bursty traffic. Experimental evaluations with synthetic and bursty traffic show that the proposed approach has less than 10% modeling error with respect to cycle-accurate NoC simulator.