Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI
Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse,, Luca Benini

TL;DR
This paper presents a real-time, predictive body-bias regulation strategy for ultra-low-power multi-core chips in 28nm UTBB FD-SOI technology, significantly improving energy efficiency and power management under environmental variations.
Contribution
It introduces a novel on-line performance measurement and predictive modeling approach for body-bias control in ULP platforms operating near-threshold.
Findings
Achieves 2x reduction in leakage power.
Improves energy consumption by 15%.
Predictive model error is reduced to 4% after calibration.
Abstract
The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected by environmental temperature and process variations. Mitigating the effect of these phenomena becomes crucial when these devices operate near-threshold, due to the magnification of process variations and to the strong temperature inversion effect that affects advanced technology nodes in low-voltage corners, which causes huge overhead due to margining for timing closure. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to maximize energy efficiency at run-time exploiting body biasing on a ULP platform operating near-threshold. The proposed method relies on on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with an on-chip…
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